- The CLED Cheat Sheet at a Glance
- Two Parts, One Credential: How CLED-1 and CLED-2 Fit Together
- Eligibility and Experience: Who Can Sit the Exam
- Domains 1 and 2: LabVIEW Real-Time and NI Scan Engine
- Domain 3: LabVIEW FPGA Must-Knows
- Domains 4 and 5: Data Communication and Hardware Synchronization
- Domain 6: Reliability, Watchdogs and Memory
- Domains 7, 8 and 9: Benchmarking, Deployment and DSC Integration
- Sequencing Your Final Review Around These Domains
- Validity, Renewal and Booking Notes
- Frequently Asked Questions
- CLED-1 is a 30-question multiple-choice exam in one hour; 70% is required to pass.
- Passing CLED-1 alone does not confer certification; CLED-2 is a separate five-hour hands-on practical.
- You need active CLD or CLA status before attempting CLED-1.
- Nine published topics cover Real-Time, Scan Engine, FPGA, communications, synchronization, reliability, benchmarking, deployment and DSC.
The CLED Cheat Sheet at a Glance
The Certified LabVIEW Embedded Systems Developer credential, issued by National Instruments (NI), is aimed at engineers who build deterministic, reliable control and monitoring systems on CompactRIO, Single-Board RIO and R Series hardware. This page condenses the facts you most need to have at your fingertips. If you want the deeper walkthrough behind any line, the CLED Study Guide 2026 and the complete guide to all 9 CLED content areas expand on each item.
| Item | CLED-1 (Part 1) | CLED-2 (Part 2) |
|---|---|---|
| Format | Multiple choice, proctored | Application-development practical, proctored |
| Length | 30 questions in one hour | Five hours |
| Passing mark | 70% | 70% |
| Hardware | None required at the exam | Single-Board RIO application development |
| Prerequisite | Active CLD or CLA status | Passing CLED-1 |
| Delivery | Per NI's current booking instructions | Onsite at NI facilities or an arranged location |
| Certificate on its own? | No | Awarded once both parts are passed |
Two Parts, One Credential: How CLED-1 and CLED-2 Fit Together
The structure is deliberately sequential. CLED-1 tests whether you understand the concepts behind embedded LabVIEW design: thread priorities, FPGA resource trade-offs, communication patterns and failure handling. CLED-2 then tests whether you can apply them under time pressure by developing an application on Single-Board RIO hardware.
What CLED-1 feels like
Thirty questions in sixty minutes leaves roughly two minutes per question. That sounds generous until you meet scenario-style items that describe a system, list its timing requirements and ask which architecture or priority assignment satisfies them. The questions reward judgment about trade-offs more than recall of dialog boxes.
What CLED-2 demands
The practical is a five-hour, hands-on application build, administered onsite at NI facilities or at an arranged location. It is not a written test and it is not graded as a topic-weighted written exam; its rubric is separate from the CLED-1 topic list. Everything you learn for Part 1 feeds into it, but it adds code quality, architecture decisions and time management on real hardware. For a sense of relative difficulty, see How Hard Is the CLED Exam?
Eligibility and Experience: Who Can Sit the Exam
- Entry for CLED-1: active Certified LabVIEW Developer (CLD) or Certified LabVIEW Architect (CLA) status.
- Entry for CLED-2: everything above, plus a passing CLED-1 result.
- Recommended experience: NI suggests 18 to 24 months developing medium-to-large LabVIEW control and monitoring applications on CompactRIO, Single-Board RIO or R Series hardware, or mastery of the relevant embedded-control training.
- Core technologies: LabVIEW, LabVIEW Real-Time and LabVIEW FPGA.
If your CLD or CLA status has lapsed, sort that out before anything else, since it gates the whole path. The CLED requirements guide covers eligibility in detail, and the pricing breakdown explains how to budget for the attempts. For official preparation material, NI points candidates to the LabVIEW for CompactRIO Developer's Guide and the CLED sample materials.
Domains 1 and 2: LabVIEW Real-Time and NI Scan Engine
Domain 1: LabVIEW Real-Time
This is the conceptual backbone of the exam. Expect questions that ask you to reason about what the scheduler will do, not just which function to drop on a diagram.
- Thread priorities, and how execution systems relate to threads and priority
- VI priority versus timed loop priority, and OS thread priority
- Priority inversion, shared resources and starvation
- Analyzing application requirements and mapping them to priorities
- Error handling and logging
- Multi-core programming
A reliable mental model: the higher-priority work must be able to preempt, but any shared resource it touches can drag its effective priority down. Whenever a question mentions a lock, a shared variable or a non-reentrant subVI used from two loops of different priority, check for priority inversion before anything else.
Domain 2: NI Scan Engine
Smaller in scope, but a dependable source of marks if you know the selection logic.
- Choosing between NI Scan Engine, Hybrid Mode and LabVIEW FPGA Mode for a given requirement
- Scan Engine timing considerations, including how scan period relates to the rest of the system
- Handling Scan Engine faults
Domain 3: LabVIEW FPGA Must-Knows
FPGA questions tend to be the most detail-heavy on the published topic list, and they reward candidates who have actually compiled designs and read the reports.
LabVIEW FPGA Topics to Master
- Emulation mode: what it verifies and what it cannot tell you about real timing
- Arbitration: how shared resources behave when multiple loops contend
- DMA FIFO buffering techniques: sizing, overflow and underflow behavior
- Fixed-point data types: choosing word length and integer word length for FPGA arithmetic
- Enable chain: how it propagates through single-cycle timed loops
- Optimization for space and for performance: throughput and single-cycle timed loops (SCTL)
- Compile report: reading it to judge whether a design will fit
The compile report appears twice in the published topics, under FPGA and again under benchmarking, which is a good hint about its importance. Be comfortable interpreting resource utilization and timing results well enough to say whether a design will fit and meet its clock target.
Domains 4 and 5: Data Communication and Hardware Synchronization
Domain 4: Data Communication
- The distinction between commands, tags and streaming data
- Best practices for tags, network streams, command/message patterns and FPGA interprocess communication
- TCP and UDP, including UDP multicast and broadcast
- Client-server architectures
The pattern to internalize is matching the mechanism to the data's nature. Lossless, ordered, high-volume data suggests streaming; latest-value status suggests tags; discrete requests that must be acknowledged suggest commands or messages. For UDP questions, remember the trade: low overhead and multicast/broadcast reach in exchange for no delivery guarantee.
Domain 5: Hardware Synchronization
- FPGA synchronization via a shared backplane bus
- Clock synchronization for distributed systems
- Identifying synchronization bottlenecks
- Time protocols: IEEE 1588, NI Time Sync and related protocols
Distributed-system questions usually hinge on which clock reference is shared and where skew can creep in. Ask yourself what each node uses as its time base and whether the scenario needs absolute time or merely relative alignment.
Domain 6: Reliability, Watchdogs and Memory
This is the longest sub-list in the published topic table, and it is where embedded thinking separates itself from desktop LabVIEW habits.
Failure Handling
- Failure modes and failure states; redundancy
- Error logging and alarming
- LabVIEW Real-Time watchdog and LabVIEW FPGA watchdog (fail-safe control architecture)
- Acknowledgement-based reliable communication
- System health monitoring and maintenance
Memory Behavior on RT Targets
- Types of memory allocation, and which components allocate memory
- Non-application consumers: DMA, drivers and TCP
- Memory fragmentation and its impact on RT targets
- Buffer allocation and its effect on memory
- What LabVIEW Real-Time does when the system runs out of memory
- Coding strategies for working with fixed-size data
Key Takeaway
A long-running controller fails differently from a desktop app: slowly, through fragmentation and unbounded growth. When a question describes a system that works for days and then degrades, think dynamic allocation in a loop, then fixed-size preallocated buffers as the remedy.
Domains 7, 8 and 9: Benchmarking, Deployment and DSC Integration
Domain 7: Test, Benchmark and Debug Applications
- Testing against functional requirements; benchmarking uptime, throughput and data rates
- Using the LabVIEW Real-Time Execution Trace Toolkit for thread, VI execution, memory allocation and resource contention analysis
- Benchmarking memory usage, CPU usage, execution time, throughput, latency, jitter and FPGA usage
- Preparing a system for benchmarking: removing unused OS components, disabling debugging, building an executable
- Debugging headless systems with console, syslog and similar tools
Domain 8: Deployment
- Creating a system image for replication; using system configuration tools
- Building an executable and setting it as the startup application
- Deploying Scan Engine and shared variable settings
- Deploying software and runtime updates, including updates applied on reboot
- Deploying and replicating touch panels
Domain 9: Integration with Other LabVIEW Modules
- Logging and displaying alarm, event and historical trend data with the LabVIEW DSC Module
Domain 9 is the narrowest topic on the list, but narrow does not mean skippable. A single DSC-focused item can be the difference at a 70% threshold, and the preparation cost is small compared with the larger domains.
Sequencing Your Final Review Around These Domains
Rather than a generic schedule, order your review by dependency. Real-Time concepts underpin almost everything else, so cover them first; reliability and memory then build directly on them. This sequence works well over a few weeks:
Scheduling foundations
- Domain 1 (priorities, execution systems, inversion)
- Domain 2 (Scan Engine mode selection and faults)
FPGA and data movement
- Domain 3 (DMA FIFOs, fixed-point, SCTL, compile report)
- Domain 4 (match mechanism to data type)
Robustness
- Domain 6 (watchdogs, memory, fragmentation)
- Domain 5 (clock sources and time protocols)
Verification and delivery
- Domains 7, 8 and 9
- Timed mixed practice under the one-hour limit using the CLED practice tests
Because NI publishes no percentage weighting for the nine topics, do not assume the largest sub-list is the largest share of questions. Spread effort sensibly and use practice results to find your weak domains. The passing score explainer clarifies how the 70% threshold applies, and the pass rate article discusses what is and is not publicly known about outcomes.
Validity, Renewal and Booking Notes
- Validity: five years from certification.
- Renewal: by retaking the CLED exam or through approved recertification-by-points activities, as set out in NI's recertification policy.
- Booking: follow NI's current registration instructions. Older badge and guide pages reference previous scheduling vendors and browser or proctor requirements; where those conflict with NI's current online-exam instructions, the current instructions win.
- Source age: the official CLED preparation guide dates from 2013, so verify any procedural detail against NI's current pages before committing to a date.
For scheduling windows see CLED Exam Dates 2026, and for the career-side question of whether the effort pays off, the ROI analysis and salary guide are the places to look. Employers who value this credential are typically those building test, measurement, industrial control and embedded monitoring systems on NI hardware, which is why the exam leans so heavily on RIO-platform behavior.
Frequently Asked Questions
No. CLED-1 is the multiple-choice prerequisite. NI awards the certification only after you also pass the separate five-hour CLED-2 practical assessment.
CLED-1 has 30 multiple-choice questions to be completed in one hour, and 70% is required to pass. CLED-2 is a separate five-hour application-development practical, also with a 70% passing mark.
You need active CLD or CLA status to attempt CLED-1, and a passing CLED-1 result before CLED-2. NI also recommends 18 to 24 months building medium-to-large control and monitoring applications on CompactRIO, Single-Board RIO or R Series hardware, or equivalent mastery of the embedded-control training.
NI publishes the nine topics without percentage weightings, so any weighting you see in practice material is an editorial estimate. The CLED-2 practical uses a separate rubric and is not a written-topic weighting scheme.
It is valid for five years. You can renew by taking the CLED exam again or through approved recertification-by-points activities under NI's recertification policy.